The present disclosure relates to a semiconductor memory device, and more particularly relates to a technique for cutting down the power dissipation of an SRAM (static random access memory).
As mobile electronic devices have become more and more popular in recent years, there have been increasing demands for reducing the power dissipation of semiconductor integrated circuits. Particularly in an ultralarge-scale semiconductor integrated circuit called “system LSI (large-scale integrated circuit),” an on-chip SRAM accounts for so large a percentage of the entire circuit that reducing the power dissipation of the SRAM will reduce the overall power dissipation of the entire system LSI chip effectively.
As a conventional SRAM, disclosed is a single-ended eight-transistor (8T)-SRAM by, for example, Toshikazu Suzuki et al. in “A Stable 2-Port SRAM Cell Design against Simultaneously Read/Write-Disturbed Accesses,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, September 2008, Vol. 43, No. 9, pp. 2109-2119.
FIG. 17 illustrates a configuration for a memory cell of an SRAM according to known art. In this memory cell 101, data is written by controlling a write word line WWL, a write bit line BL and an inverted write bit line BLX, and data is read by controlling a read word line RWL and a read bit line RBL.
While data is being read, the read bit line RBL is precharged, and the read word line RWL is driven to turn a transistor T2 ON. After that, when a transistor T1 turns ON, for example, depending on the data stored in this memory cell 101, the read bit line RBL is connected to a ground potential. As a result, the data requested is read out.
In general, an SRAM is comprised of a plurality of memory cells 101 that are arranged in columns and rows to form a matrix pattern, and each read word line RWL is connected to an associated row of memory cells including a selected memory cell. Thus, in an SRAM comprised of memory cells 101 each having the configuration shown in FIG. 17, when a read word line RWL is driven, the transistors T1 and T2 may both turn ON in each of a plurality of memory cells connected to that read word line RWL. In that case, in an SRAM comprised of memory cells 101 each having the configuration shown in FIG. 17, no matter whether a given memory cell is a selected memory cell or a non-selected one, the read bit line RBL connected to those memory cells may be discharged to the ground potential.
As a result, in every data read cycle, the read bit lines RBL connected to non-selected memory cells need to be discharged and precharged, thus possibly increasing the power dissipation. Particularly when the number of memory cells increases, the power dissipation rises significantly.
In view of the foregoing background, it is therefore an object of the present disclosure to provide a semiconductor memory device which allows for cutting down the power dissipation even if the number of memory cells increases.